1. Field of the Invention
The invention relates to an analog to digital converter, and more particularly, to a folding analog to digital converter capable of calibration and method thereof.
2. Description of the Prior Art
Analog to digital converters (ADCs) allow the use of sophisticated digital signal processing systems to process analog signals, which are common in the real world. High-speed ADCs are critical components of digital signal processing systems.
Flash type ADCs are commonly used for high speed signal applications. In a flash type ADC, a separate comparator is used for each possible output code bit, and this parallelism is what gives the flash ADC its speed. However, because the number of comparators grows exponentially with the resolution of the ADC, flash type ADCs have high power consumption and large integrated circuit (IC) chip area. These characteristics make flash type ADCs undesirable for low power portable applications.
Folding and interpolating ADCs have been widely used to overcome these power and IC area limitations of the flash type ADC. In a flash type ADC, at any time, only the comparators around the transition voltage provide useful information. Folding and interpolating ADCs exploit this fact to reduce the number of comparators, and thereby have a relatively low power consumption and smaller IC area when compared with flash based ADCs. In a folding and interpolating ADC, each comparator is connected to a group of amplifiers, also referred to as a folder.
FIG. 1 shows a conventional folding ADC 100. The folding ADC 100 receives an analog input voltage Vin, and generates a corresponding differential output voltage comprising a first output voltage Vout1 and a second output voltage Vout2. A first and a second pull-up resistor 102 and 104 connect the first output voltage Vout1 and the second output voltage Vout2 to a power supply node VDD, respectively. Additionally, the folding ADC 100 includes three differential amplifiers 106. Each amplifier 106 receives the input voltage Vin and one of a plurality of different reference voltages, Vref1, Vref2, and Vref3, and includes two transistors and a current source. In the folding ADC 100, the amplifiers receiving the odd numbered reference voltages (ex: Vref1 and Vref3 in FIG. 1) are connected in the same way as the first amplifier, which receives the reference voltage of Vref1. The amplifier receiving the even numbered reference voltage (ex: Vref2 in FIG. 1), has the connections for outputting the first output voltage Vout1 and the second output voltage Vout2 reversed, as shown in FIG. 1.
FIG. 2 shows the differential output voltage Vout of the folding ADC 100. The output voltage Vout of the folding ADC 100 is a differential signal comprising the first output voltage Vout1 and the second output voltage Vout2 in FIG. 1. In FIG. 2, the ideal output voltage 206 has a zero crossing at each reference voltage (Vref1, Vref2, and Vref3). Because the amplifiers 106 have alternating connections to the first output voltage Vout1 and the second output voltage Vout2, the ideal differential output voltage 206 swings from positive to negative and vice versa as the input voltage crosses over each reference voltage. In the ideal situation, the first pull-up resistor 102 would be of the same value as the second pull-up resistor 104, and all the amplifiers 106 in the folding ADC 100 would be perfectly matched with each other. More specifically, both transistors 108, 112 in each amplifier would have equal characteristics such as threshold voltage, and each current source 110 would draw the same bias current through the amplifier 106. Of course, in the practice, due to process variations, for example, there are always slight variations between devices. The pull-up resistors 102,104 will not be of exactly the same value, the transistors 108,112 will not be perfectly matched, and there will be slight differences between the amounts of current drawn by each current source 110. Thus, as represented by the dotted line 202 in FIG. 2, the curve of FIG. 2 may deviate from the ideal output voltage 206.
These imperfect characteristics of the amplifiers and pull-up resistors may reduce the linearity of the ADC. This is a serious problem and several correction methods have been proposed. One common method of dealing with the non-linearity is to implement a digital correction function to correct the output of the ADC. During calibration, a function generator can be used to provide a set of known input voltages. For each input voltage, the output of the ADC is recorded. A mapping function converting the output of this particular ADC to the correct digital output value can then be formulated. This correction method, however, has several disadvantages including requiring a function generator to provide the input signal during calibration, as well as additional hardware or software cycles to map the output of the ADC to the correct digital value.